Design and evaluation of a thread-level speculation runtime library

  1. Estébanez López, Álvaro
Supervised by:
  1. Diego R. Llanos Director

Defence university: Universidad de Valladolid

Fecha de defensa: 13 January 2016

  1. Francisco Almeida Rodriguez Chair
  2. Julio Ortega Lopera Secretary
  3. Fernando Guirado Fernández Committee member
  4. Katzalin Olcoz Committee member
  5. Juan Manuel Orduña Huertas Committee member
  1. Computing (Architecture and Technology of Computers. Computational Science and Artificial Intelligence. Computing System

Type: Thesis


ABSTRACT It is very likely that, in the next years, shared-memory systems with hundreds or even thousands of computational units will become commonplace. Since parallel programming is conceptually difficult, and to take advantage of these platforms, it is desirable to have compiling and/or runtime systems that automatically extract all the available parallelism of a sequential application. Although many parallel processing approaches have been developed in the last decades, most automatic parallelization proposals are focused on codes with no hurdles. Speculative parallelization (SP) techniques arise as a more general solution, allowing the parallel execution of any code, even in the presence of dependence violations. To ensure that, SP approaches rely on a runtime monitor responsible for ensuring that the results of the parallel execution match the expected output of the original, sequential code. This technique, based on the optimistic assumption that no dependences will arise when executing the code in parallel, launches threads that execute different fragments of the sequential code at the same time. If a dependence violation is detected, the offending threads are stopped and restarted with the correct values, thus ensuring that the execution follows sequential semantics. Our contribution in this field includes (1) a new, easy-to-use speculative runtime library; (2) new proposals which allow to decrease the number of memory accesses involved in speculative operations, as well as some advice to decrement the memory footprint; (3) research on new scheduling methods focused on the dynamic management of chunks of iterations in speculative executions; (4) an hybrid approach which implements speculative parallelism using transactional memory to handle its critical sections; and (5) an analysis of the speculative techniques in one of the most state-of-the-art devices as are Intel Xeon Phi coprocessors. Speculative parallelization is a lively research field. Our results show that these techniques have the potential of leading to considerable improvements in the performance of many applications.We expect that this work, among others, will foster the use of SP-based solutions in commercial compilers and shared-memory parallel programming models.