A PLL-based synthesizer for tunable digital clock generation in a continuous-time Σ Δ A/D converter

  1. Segundo, J.
  2. Quintanilla, L.
  3. Arias, J.
  4. Enríquez, L.
  5. Hernández, J.M.
  6. Vicente, J.
Revue:
Integration, the VLSI Journal

ISSN: 0167-9260

Année de publication: 2009

Volumen: 42

Número: 1

Pages: 24-33

Type: Article

DOI: 10.1016/J.VLSI.2008.07.002 GOOGLE SCHOLAR

Objectifs de Développement Durable

La source de données: Scopus